library IEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use  IEEE.STD_LOGIC_ARITH.all;

use work.package_sumador.all;

entity sumador is
	generic(GND			: std_logic_vector (7 downto 0) := "00000000"
		   );
	port(a,b,p,q       : in	std_logic_vector (7 downto 0);
		 s, d		   : out std_logic_vector (7 downto 0);
		 clk,rst	   : in std_logic
		 );
end sumador;

architecture sum_arch of sumador is
	signal e1a : std_logic_vector(7 downto 0);
	signal e1b : std_logic_vector(7 downto 0);
	signal e1c : std_logic_vector(7 downto 0);
	signal e2a : std_logic_vector(7 downto 0);
	signal e2b : std_logic_vector(7 downto 0);
	signal s2b : std_logic_vector(7 downto 0);
	signal e3a : std_logic_vector(7 downto 0);
	signal e3b : integer;
	signal e3c : std_logic_vector(7 downto 0);
	signal s3c : std_logic_vector(7 downto 0);
	signal diff_exp : integer;
	signal maxpq : std_logic;
	signal minab : std_logic_vector(7 downto 0);
	signal ent1 : std_logic_vector(7 downto 0);
	signal ent2 : std_logic_vector(7 downto 0);
	signal sum_ent1 : std_logic_vector(7 downto 0);
	signal sum_ent2 : std_logic_vector(7 downto 0);
	

	

begin
	comp_exp:sum_exp port map (p, q, e1a, diff_exp, maxpq);
	sel_frac:selector_fraccion port map (a, b, maxpq, minab, e1b);
	despl_der:desplazador port map (minab, '0', diff_exp, e1c);
	------------------------------------------------------------------------
	r1a:reg_8 port map (e1a, clk, rst, e2a);
	r1b:reg_8 port map (e1b, clk, rst, ent1);
	r1c:reg_8 port map (e1c, clk, rst, ent2);
	------------------------------------------------------------------------
	e2b <= (ent1 + ent2);
	r2a:reg_8 port map (e2a, clk, rst, e3a);
	r2b:reg_8 port map (e2b, clk, rst, s2b);
	------------------------------------------------------------------------
	cont_ceros:cont_ceros_significativos port map(s2b, e3b);
	desp_izq: desplazador port map (s2b, '1', e3b, e3c);
	------------------------------------------------------------------------
	r3a:reg_8 port map (e3a, clk, rst, sum_ent1);
	r3b:reg_8 port map (conv_std_logic_vector(e3b, 8), clk, rst, sum_ent2);
	r3c:reg_8 port map (e3c, clk, rst, s3c);
	------------------------------------------------------------------------
	
	s <= (sum_ent1 + sum_ent2);
	d <= s3c;
	
end sum_arch;